Post-Moore: Prospects for Novel Patterning of Low Volume ICs
Dr. Mike Fritze, VP
Potomac Institute for Policy Studies
Keynote Talk for the 2021 SPIE Advanced Lithography Conference
Novel Patterning Technologies Section
Feb 22-26, 2021 (Virtual)
Summary: The end of the 50-year-long Moore’s Law based physical scaling of semiconductor chips represents a major paradigm shift. Along with technological implications, this major inflection point will usher in an era of substantially new business models in the worldwide semiconductor industry. Future performance gains will be made by clever design and architecture developments, not physical scaling of chips. This means than we will see an increased trend of design customization to a particular function.
The old business model was based on increasingly more expensive fabrication facilities which had to produce parts in very high volumes to be cost-effective. Fairly generic chip types were made in very high volumes and utilized by the major system companies. The new model will be driven by a shift to a larger variety of custom chips made in smaller volumes. The big system companies are realizing this trend towards customization and developing their own internal designs to differentiate themselves with performance gains. This is a major business model shift from the past, where these companies bought outside generic parts and adapted them to their needs.
This big change is simply a sign of the maturing semiconductor industry. Value add and profit potential will now be dominated by those organizations that can execute clever new designs and integrate a variety of chip technologies into a custom advanced package. Some legacy companies may shift their strategies accordingly to adapt, but new companies will undoubtably be formed to take advantage of these new opportunities. This is a particularly attractive time for smaller new entrants in this field. There will likely be specialist “integration” fabs whose main role will be to integrate chips made in various technologies. The concept of “hardware as a service” will also see increasing traction.
We are already seeing a resurgence of the trend towards more custom ASIC chips for example. The key challenge here is to lower the costs of customization which are very high at the lower volume range of interest today. This presents new opportunities to optimize low volume fabrication via implementation of direct write and other lower volume process strategies.
The major paradigm shift we are currently undergoing in the semiconductor industry will provide many new opportunities for companies that are innovative and flexible particularly in the design, architecture and integration areas. The increased interest in higher mix lower volume custom chips will drive entirely new fabrication flows based on new technologies. Finally, this shift represents a move towards more common interests between industry and the US Government/DoD. This new overlap will help spawn productive public-private partnerships which will help industry develop new technologies and provide the US Government/DoD with desirable access paths for these.